Linux anchor 4.4.0-210-generic #242-Ubuntu SMP Fri Apr 16 09:57:56 UTC 2021 x86_64
Apache/2.4.18 (Ubuntu)
Server IP : 10.10.100.4 & Your IP : 216.73.217.150
Domains :
Cant Read [ /etc/named.conf ]
User : www-data
Terminal
Auto Root
Create File
Create Folder
Localroot Suggester
Backdoor Destroyer
Readme
/
usr /
include /
linux /
Delete
Unzip
Name
Size
Permission
Date
Action
android
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
byteorder
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
caif
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
can
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
dvb
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
hdlc
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
hsi
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
iio
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
isdn
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
mmc
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
netfilter
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
netfilter_arp
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
netfilter_bridge
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
netfilter_ipv4
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
netfilter_ipv6
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
nfsd
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
raid
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
spi
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
sunrpc
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
tc_act
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
tc_ematch
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
usb
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
wimax
[ DIR ]
drwxr-xr-x
2021-04-21 07:31
a.out.h
7.15
KB
-rw-r--r--
2021-04-16 13:31
acct.h
3.58
KB
-rw-r--r--
2021-04-16 13:31
adb.h
1.05
KB
-rw-r--r--
2021-04-16 13:31
adfs_fs.h
873
B
-rw-r--r--
2021-04-16 13:31
affs_hardblocks.h
1.45
KB
-rw-r--r--
2021-04-16 13:31
agpgart.h
3.83
KB
-rw-r--r--
2021-04-16 13:31
aio_abi.h
3.1
KB
-rw-r--r--
2021-04-16 13:31
am437x-vpfe.h
3.53
KB
-rw-r--r--
2021-04-16 13:31
apm_bios.h
3.53
KB
-rw-r--r--
2021-04-16 13:31
arcfb.h
150
B
-rw-r--r--
2021-04-16 13:31
atalk.h
960
B
-rw-r--r--
2021-04-16 13:31
atm.h
7.64
KB
-rw-r--r--
2021-04-16 13:31
atm_eni.h
585
B
-rw-r--r--
2021-04-16 13:31
atm_he.h
343
B
-rw-r--r--
2021-04-16 13:31
atm_idt77105.h
892
B
-rw-r--r--
2021-04-16 13:31
atm_nicstar.h
1.19
KB
-rw-r--r--
2021-04-16 13:31
atm_tcp.h
1.52
KB
-rw-r--r--
2021-04-16 13:31
atm_zatm.h
1.44
KB
-rw-r--r--
2021-04-16 13:31
atmapi.h
889
B
-rw-r--r--
2021-04-16 13:31
atmarp.h
1.2
KB
-rw-r--r--
2021-04-16 13:31
atmbr2684.h
3.13
KB
-rw-r--r--
2021-04-16 13:31
atmclip.h
513
B
-rw-r--r--
2021-04-16 13:31
atmdev.h
7.44
KB
-rw-r--r--
2021-04-16 13:31
atmioc.h
1.55
KB
-rw-r--r--
2021-04-16 13:31
atmlec.h
2.26
KB
-rw-r--r--
2021-04-16 13:31
atmmpc.h
4.07
KB
-rw-r--r--
2021-04-16 13:31
atmppp.h
576
B
-rw-r--r--
2021-04-16 13:31
atmsap.h
4.79
KB
-rw-r--r--
2021-04-16 13:31
atmsvc.h
1.75
KB
-rw-r--r--
2021-04-16 13:31
audit.h
18.2
KB
-rw-r--r--
2021-04-16 13:31
aufs_type.h
10.35
KB
-rw-r--r--
2021-04-16 13:31
auto_fs.h
2.23
KB
-rw-r--r--
2021-04-16 13:31
auto_fs4.h
4.03
KB
-rw-r--r--
2021-04-16 13:31
auxvec.h
1.4
KB
-rw-r--r--
2021-04-16 13:31
ax25.h
2.7
KB
-rw-r--r--
2021-04-16 13:31
b1lli.h
1.62
KB
-rw-r--r--
2021-04-16 13:31
baycom.h
820
B
-rw-r--r--
2021-04-16 13:31
bcm933xx_hcs.h
356
B
-rw-r--r--
2021-04-16 13:31
bfs_fs.h
1.79
KB
-rw-r--r--
2021-04-16 13:31
binfmts.h
565
B
-rw-r--r--
2021-04-16 13:31
blkpg.h
1.53
KB
-rw-r--r--
2021-04-16 13:31
blktrace_api.h
4.38
KB
-rw-r--r--
2021-04-16 13:31
bpf.h
8.22
KB
-rw-r--r--
2021-04-16 13:31
bpf_common.h
1.2
KB
-rw-r--r--
2021-04-16 13:31
bpqether.h
952
B
-rw-r--r--
2021-04-16 13:31
bsg.h
2.37
KB
-rw-r--r--
2021-04-16 13:31
btrfs.h
20.16
KB
-rw-r--r--
2021-04-16 13:31
can.h
7.62
KB
-rw-r--r--
2021-04-16 13:31
capability.h
11.46
KB
-rw-r--r--
2021-04-16 13:31
capi.h
2.99
KB
-rw-r--r--
2021-04-16 13:31
cciss_defs.h
3.14
KB
-rw-r--r--
2021-04-16 13:31
cciss_ioctl.h
2.63
KB
-rw-r--r--
2021-04-16 13:31
cdrom.h
28.12
KB
-rw-r--r--
2021-04-16 13:31
cgroupstats.h
2.1
KB
-rw-r--r--
2021-04-16 13:31
chio.h
5.16
KB
-rw-r--r--
2021-04-16 13:31
cm4000_cs.h
1.7
KB
-rw-r--r--
2021-04-16 13:31
cn_proc.h
3.19
KB
-rw-r--r--
2021-04-16 13:31
coda.h
17.09
KB
-rw-r--r--
2021-04-16 13:31
coda_psdev.h
297
B
-rw-r--r--
2021-04-16 13:31
coff.h
12.12
KB
-rw-r--r--
2021-04-16 13:31
connector.h
2.14
KB
-rw-r--r--
2021-04-16 13:31
const.h
872
B
-rw-r--r--
2021-04-16 13:31
cramfs_fs.h
2.68
KB
-rw-r--r--
2021-04-16 13:31
cuda.h
842
B
-rw-r--r--
2021-04-16 13:31
cyclades.h
16.65
KB
-rw-r--r--
2021-04-16 13:31
cycx_cfm.h
2.86
KB
-rw-r--r--
2021-04-16 13:31
dcbnl.h
24.27
KB
-rw-r--r--
2021-04-16 13:31
dccp.h
6.22
KB
-rw-r--r--
2021-04-16 13:31
dlm.h
2.43
KB
-rw-r--r--
2021-04-16 13:31
dlm_device.h
2.42
KB
-rw-r--r--
2021-04-16 13:31
dlm_netlink.h
1.04
KB
-rw-r--r--
2021-04-16 13:31
dlm_plock.h
831
B
-rw-r--r--
2021-04-16 13:31
dlmconstants.h
4.9
KB
-rw-r--r--
2021-04-16 13:31
dm-ioctl.h
10.45
KB
-rw-r--r--
2021-04-16 13:31
dm-log-userspace.h
14.82
KB
-rw-r--r--
2021-04-16 13:31
dn.h
4.47
KB
-rw-r--r--
2021-04-16 13:31
dqblk_xfs.h
8.65
KB
-rw-r--r--
2021-04-16 13:31
edd.h
5.41
KB
-rw-r--r--
2021-04-16 13:31
efs_fs_sb.h
2.11
KB
-rw-r--r--
2021-04-16 13:31
elf-em.h
2.17
KB
-rw-r--r--
2021-04-16 13:31
elf-fdpic.h
1.04
KB
-rw-r--r--
2021-04-16 13:31
elf.h
11.64
KB
-rw-r--r--
2021-04-16 13:31
elfcore.h
2.86
KB
-rw-r--r--
2021-04-16 13:31
errno.h
23
B
-rw-r--r--
2021-04-16 13:31
errqueue.h
1.21
KB
-rw-r--r--
2021-04-16 13:31
ethtool.h
64.1
KB
-rw-r--r--
2021-04-16 13:31
eventpoll.h
2.32
KB
-rw-r--r--
2021-04-16 13:31
fadvise.h
779
B
-rw-r--r--
2021-04-16 13:31
falloc.h
2.72
KB
-rw-r--r--
2021-04-16 13:31
fanotify.h
3.42
KB
-rw-r--r--
2021-04-16 13:31
fb.h
16
KB
-rw-r--r--
2021-04-16 13:31
fcntl.h
2.16
KB
-rw-r--r--
2021-04-16 13:31
fd.h
11.34
KB
-rw-r--r--
2021-04-16 13:31
fdreg.h
5.23
KB
-rw-r--r--
2021-04-16 13:31
fib_rules.h
1.58
KB
-rw-r--r--
2021-04-16 13:31
fiemap.h
2.65
KB
-rw-r--r--
2021-04-16 13:31
filter.h
2.1
KB
-rw-r--r--
2021-04-16 13:31
firewire-cdev.h
42.86
KB
-rw-r--r--
2021-04-16 13:31
firewire-constants.h
3.16
KB
-rw-r--r--
2021-04-16 13:31
flat.h
2.04
KB
-rw-r--r--
2021-04-16 13:31
fou.h
631
B
-rw-r--r--
2021-04-16 13:31
fs.h
8.21
KB
-rw-r--r--
2021-04-16 13:31
fsl_hypervisor.h
7.05
KB
-rw-r--r--
2021-04-16 13:31
fuse.h
16.34
KB
-rw-r--r--
2021-04-16 13:31
futex.h
4.81
KB
-rw-r--r--
2021-04-16 13:31
gameport.h
834
B
-rw-r--r--
2021-04-16 13:31
gen_stats.h
1.46
KB
-rw-r--r--
2021-04-16 13:31
genetlink.h
1.77
KB
-rw-r--r--
2021-04-16 13:31
gfs2_ondisk.h
11.91
KB
-rw-r--r--
2021-04-16 13:31
gigaset_dev.h
1.35
KB
-rw-r--r--
2021-04-16 13:31
gsmmux.h
978
B
-rw-r--r--
2021-04-16 13:31
hdlc.h
574
B
-rw-r--r--
2021-04-16 13:31
hdlcdrv.h
2.78
KB
-rw-r--r--
2021-04-16 13:31
hdreg.h
22.11
KB
-rw-r--r--
2021-04-16 13:31
hid.h
1.79
KB
-rw-r--r--
2021-04-16 13:31
hiddev.h
6.13
KB
-rw-r--r--
2021-04-16 13:31
hidraw.h
1.41
KB
-rw-r--r--
2021-04-16 13:31
hpet.h
680
B
-rw-r--r--
2021-04-16 13:31
hsr_netlink.h
1017
B
-rw-r--r--
2021-04-16 13:31
hw_breakpoint.h
575
B
-rw-r--r--
2021-04-16 13:31
hyperv.h
10.26
KB
-rw-r--r--
2021-04-16 13:31
hysdn_if.h
1.29
KB
-rw-r--r--
2021-04-16 13:31
i2c-dev.h
2.49
KB
-rw-r--r--
2021-04-16 13:31
i2c.h
6.65
KB
-rw-r--r--
2021-04-16 13:31
i2o-dev.h
11.22
KB
-rw-r--r--
2021-04-16 13:31
i8k.h
1.43
KB
-rw-r--r--
2021-04-16 13:31
icmp.h
2.82
KB
-rw-r--r--
2021-04-16 13:31
icmpv6.h
3.82
KB
-rw-r--r--
2021-04-16 13:31
if.h
10.45
KB
-rw-r--r--
2021-04-16 13:31
if_addr.h
1.7
KB
-rw-r--r--
2021-04-16 13:31
if_addrlabel.h
658
B
-rw-r--r--
2021-04-16 13:31
if_alg.h
882
B
-rw-r--r--
2021-04-16 13:31
if_arcnet.h
3.57
KB
-rw-r--r--
2021-04-16 13:31
if_arp.h
6.24
KB
-rw-r--r--
2021-04-16 13:31
if_bonding.h
4.11
KB
-rw-r--r--
2021-04-16 13:31
if_bridge.h
4.46
KB
-rw-r--r--
2021-04-16 13:31
if_cablemodem.h
922
B
-rw-r--r--
2021-04-16 13:31
if_eql.h
1.26
KB
-rw-r--r--
2021-04-16 13:31
if_ether.h
7.13
KB
-rw-r--r--
2021-04-16 13:31
if_fc.h
1.63
KB
-rw-r--r--
2021-04-16 13:31
if_fddi.h
3.6
KB
-rw-r--r--
2021-04-16 13:31
if_frad.h
2.89
KB
-rw-r--r--
2021-04-16 13:31
if_hippi.h
4.07
KB
-rw-r--r--
2021-04-16 13:31
if_infiniband.h
1.13
KB
-rw-r--r--
2021-04-16 13:31
if_link.h
16.74
KB
-rw-r--r--
2021-04-16 13:31
if_ltalk.h
147
B
-rw-r--r--
2021-04-16 13:31
if_packet.h
7.63
KB
-rw-r--r--
2021-04-16 13:31
if_phonet.h
361
B
-rw-r--r--
2021-04-16 13:31
if_plip.h
596
B
-rw-r--r--
2021-04-16 13:31
if_ppp.h
29
B
-rw-r--r--
2021-04-16 13:31
if_pppol2tp.h
3.11
KB
-rw-r--r--
2021-04-16 13:31
if_pppox.h
4.64
KB
-rw-r--r--
2021-04-16 13:31
if_slip.h
809
B
-rw-r--r--
2021-04-16 13:31
if_team.h
2.48
KB
-rw-r--r--
2021-04-16 13:31
if_tun.h
3.72
KB
-rw-r--r--
2021-04-16 13:31
if_tunnel.h
3.14
KB
-rw-r--r--
2021-04-16 13:31
if_vlan.h
1.69
KB
-rw-r--r--
2021-04-16 13:31
if_x25.h
817
B
-rw-r--r--
2021-04-16 13:31
igmp.h
2.88
KB
-rw-r--r--
2021-04-16 13:31
ila.h
220
B
-rw-r--r--
2021-04-16 13:31
in.h
9.38
KB
-rw-r--r--
2021-04-16 13:31
in6.h
7.08
KB
-rw-r--r--
2021-04-16 13:31
in_route.h
873
B
-rw-r--r--
2021-04-16 13:31
inet_diag.h
2.78
KB
-rw-r--r--
2021-04-16 13:31
inotify.h
2.85
KB
-rw-r--r--
2021-04-16 13:31
input-event-codes.h
22.72
KB
-rw-r--r--
2021-04-16 13:31
input.h
14.7
KB
-rw-r--r--
2021-04-16 13:31
ioctl.h
100
B
-rw-r--r--
2021-04-16 13:31
ip.h
4.45
KB
-rw-r--r--
2021-04-16 13:31
ip6_tunnel.h
1.67
KB
-rw-r--r--
2021-04-16 13:31
ip_vs.h
13.23
KB
-rw-r--r--
2021-04-16 13:31
ipc.h
1.99
KB
-rw-r--r--
2021-04-16 13:31
ipmi.h
15.8
KB
-rw-r--r--
2021-04-16 13:31
ipmi_msgdefs.h
4.37
KB
-rw-r--r--
2021-04-16 13:31
ipsec.h
884
B
-rw-r--r--
2021-04-16 13:31
ipv6.h
3.45
KB
-rw-r--r--
2021-04-16 13:31
ipv6_route.h
1.73
KB
-rw-r--r--
2021-04-16 13:31
ipx.h
1.79
KB
-rw-r--r--
2021-04-16 13:31
irda.h
7.31
KB
-rw-r--r--
2021-04-16 13:31
irqnr.h
104
B
-rw-r--r--
2021-04-16 13:31
isdn.h
5.58
KB
-rw-r--r--
2021-04-16 13:31
isdn_divertif.h
1.11
KB
-rw-r--r--
2021-04-16 13:31
isdn_ppp.h
1.82
KB
-rw-r--r--
2021-04-16 13:31
isdnif.h
2.25
KB
-rw-r--r--
2021-04-16 13:31
iso_fs.h
6.29
KB
-rw-r--r--
2021-04-16 13:31
ivtv.h
2.89
KB
-rw-r--r--
2021-04-16 13:31
ivtvfb.h
1.12
KB
-rw-r--r--
2021-04-16 13:31
ixjuser.h
24.53
KB
-rw-r--r--
2021-04-16 13:31
jffs2.h
6.85
KB
-rw-r--r--
2021-04-16 13:31
joystick.h
3.5
KB
-rw-r--r--
2021-04-16 13:31
kcmp.h
214
B
-rw-r--r--
2021-04-16 13:31
kd.h
6.07
KB
-rw-r--r--
2021-04-16 13:31
kdev_t.h
320
B
-rw-r--r--
2021-04-16 13:31
kernel-page-flags.h
814
B
-rw-r--r--
2021-04-16 13:31
kernel.h
315
B
-rw-r--r--
2021-04-16 13:31
kernelcapi.h
956
B
-rw-r--r--
2021-04-16 13:31
kexec.h
1.69
KB
-rw-r--r--
2021-04-16 13:31
keyboard.h
12.42
KB
-rw-r--r--
2021-04-16 13:31
keyctl.h
2.98
KB
-rw-r--r--
2021-04-16 13:31
kvm.h
36.02
KB
-rw-r--r--
2021-04-16 13:31
kvm_para.h
760
B
-rw-r--r--
2021-04-16 13:31
l2tp.h
5.4
KB
-rw-r--r--
2021-04-16 13:31
libc-compat.h
6.15
KB
-rw-r--r--
2021-04-16 13:31
limits.h
874
B
-rw-r--r--
2021-04-16 13:31
llc.h
2.98
KB
-rw-r--r--
2021-04-16 13:31
loop.h
2.36
KB
-rw-r--r--
2021-04-16 13:31
lp.h
3.72
KB
-rw-r--r--
2021-04-16 13:31
lwtunnel.h
774
B
-rw-r--r--
2021-04-16 13:31
magic.h
2.85
KB
-rw-r--r--
2021-04-16 13:31
major.h
4.53
KB
-rw-r--r--
2021-04-16 13:31
map_to_7segment.h
7.02
KB
-rw-r--r--
2021-04-16 13:31
matroxfb.h
1.37
KB
-rw-r--r--
2021-04-16 13:31
mdio.h
13.74
KB
-rw-r--r--
2021-04-16 13:31
media-bus-format.h
5.47
KB
-rw-r--r--
2021-04-16 13:31
media.h
4.98
KB
-rw-r--r--
2021-04-16 13:31
mei.h
4.62
KB
-rw-r--r--
2021-04-16 13:31
membarrier.h
2.38
KB
-rw-r--r--
2021-04-16 13:31
memfd.h
186
B
-rw-r--r--
2021-04-16 13:31
mempolicy.h
2.35
KB
-rw-r--r--
2021-04-16 13:31
meye.h
2.41
KB
-rw-r--r--
2021-04-16 13:31
mic_common.h
6.3
KB
-rw-r--r--
2021-04-16 13:31
mic_ioctl.h
2.14
KB
-rw-r--r--
2021-04-16 13:31
mii.h
7.76
KB
-rw-r--r--
2021-04-16 13:31
minix_fs.h
2.01
KB
-rw-r--r--
2021-04-16 13:31
mman.h
230
B
-rw-r--r--
2021-04-16 13:31
mmtimer.h
2.01
KB
-rw-r--r--
2021-04-16 13:31
mpls.h
1.38
KB
-rw-r--r--
2021-04-16 13:31
mpls_iptunnel.h
650
B
-rw-r--r--
2021-04-16 13:31
mqueue.h
2.06
KB
-rw-r--r--
2021-04-16 13:31
mroute.h
4.12
KB
-rw-r--r--
2021-04-16 13:31
mroute6.h
4.19
KB
-rw-r--r--
2021-04-16 13:31
msdos_fs.h
6.74
KB
-rw-r--r--
2021-04-16 13:31
msg.h
3.21
KB
-rw-r--r--
2021-04-16 13:31
mtio.h
7.92
KB
-rw-r--r--
2021-04-16 13:31
n_r3964.h
2.29
KB
-rw-r--r--
2021-04-16 13:31
nbd.h
2.3
KB
-rw-r--r--
2021-04-16 13:31
ncp.h
4.94
KB
-rw-r--r--
2021-04-16 13:31
ncp_fs.h
3.27
KB
-rw-r--r--
2021-04-16 13:31
ncp_mount.h
2.06
KB
-rw-r--r--
2021-04-16 13:31
ncp_no.h
651
B
-rw-r--r--
2021-04-16 13:31
ndctl.h
5.13
KB
-rw-r--r--
2021-04-16 13:31
neighbour.h
4.11
KB
-rw-r--r--
2021-04-16 13:31
net.h
1.97
KB
-rw-r--r--
2021-04-16 13:31
net_dropmon.h
1.07
KB
-rw-r--r--
2021-04-16 13:31
net_namespace.h
609
B
-rw-r--r--
2021-04-16 13:31
net_tstamp.h
3.55
KB
-rw-r--r--
2021-04-16 13:31
netconf.h
485
B
-rw-r--r--
2021-04-16 13:31
netdevice.h
2.14
KB
-rw-r--r--
2021-04-16 13:31
netfilter.h
1.69
KB
-rw-r--r--
2021-04-16 13:31
netfilter_arp.h
380
B
-rw-r--r--
2021-04-16 13:31
netfilter_bridge.h
768
B
-rw-r--r--
2021-04-16 13:31
netfilter_decnet.h
1.83
KB
-rw-r--r--
2021-04-16 13:31
netfilter_ipv4.h
2.02
KB
-rw-r--r--
2021-04-16 13:31
netfilter_ipv6.h
2.04
KB
-rw-r--r--
2021-04-16 13:31
netlink.h
5.8
KB
-rw-r--r--
2021-04-16 13:31
netlink_diag.h
1.05
KB
-rw-r--r--
2021-04-16 13:31
netrom.h
744
B
-rw-r--r--
2021-04-16 13:31
nfc.h
10.84
KB
-rw-r--r--
2021-04-16 13:31
nfs.h
4.31
KB
-rw-r--r--
2021-04-16 13:31
nfs2.h
1.37
KB
-rw-r--r--
2021-04-16 13:31
nfs3.h
2.24
KB
-rw-r--r--
2021-04-16 13:31
nfs4.h
6.08
KB
-rw-r--r--
2021-04-16 13:31
nfs4_mount.h
1.83
KB
-rw-r--r--
2021-04-16 13:31
nfs_fs.h
1.51
KB
-rw-r--r--
2021-04-16 13:31
nfs_idmap.h
2.19
KB
-rw-r--r--
2021-04-16 13:31
nfs_mount.h
2.32
KB
-rw-r--r--
2021-04-16 13:31
nfsacl.h
605
B
-rw-r--r--
2021-04-16 13:31
nl80211.h
190.47
KB
-rw-r--r--
2021-04-16 13:31
nubus.h
8.17
KB
-rw-r--r--
2021-04-16 13:31
nvme_ioctl.h
1.51
KB
-rw-r--r--
2021-04-16 13:31
nvram.h
469
B
-rw-r--r--
2021-04-16 13:31
omap3isp.h
20.19
KB
-rw-r--r--
2021-04-16 13:31
omapfb.h
5.72
KB
-rw-r--r--
2021-04-16 13:31
oom.h
448
B
-rw-r--r--
2021-04-16 13:31
openvswitch.h
26.79
KB
-rw-r--r--
2021-04-16 13:31
packet_diag.h
1.57
KB
-rw-r--r--
2021-04-16 13:31
param.h
78
B
-rw-r--r--
2021-04-16 13:31
parport.h
3.56
KB
-rw-r--r--
2021-04-16 13:31
patchkey.h
829
B
-rw-r--r--
2021-04-16 13:31
pci.h
1.29
KB
-rw-r--r--
2021-04-16 13:31
pci_regs.h
47.93
KB
-rw-r--r--
2021-04-16 13:31
perf_event.h
27.45
KB
-rw-r--r--
2021-04-16 13:31
personality.h
1.99
KB
-rw-r--r--
2021-04-16 13:31
pfkeyv2.h
10.26
KB
-rw-r--r--
2021-04-16 13:31
pg.h
2.23
KB
-rw-r--r--
2021-04-16 13:31
phantom.h
1.55
KB
-rw-r--r--
2021-04-16 13:31
phonet.h
4.51
KB
-rw-r--r--
2021-04-16 13:31
pkt_cls.h
8.04
KB
-rw-r--r--
2021-04-16 13:31
pkt_sched.h
19.19
KB
-rw-r--r--
2021-04-16 13:31
pktcdvd.h
2.56
KB
-rw-r--r--
2021-04-16 13:31
pmu.h
5.13
KB
-rw-r--r--
2021-04-16 13:31
poll.h
22
B
-rw-r--r--
2021-04-16 13:31
posix_types.h
1.01
KB
-rw-r--r--
2021-04-16 13:31
ppdev.h
3.07
KB
-rw-r--r--
2021-04-16 13:31
ppp-comp.h
2.41
KB
-rw-r--r--
2021-04-16 13:31
ppp-ioctl.h
5.29
KB
-rw-r--r--
2021-04-16 13:31
ppp_defs.h
4.93
KB
-rw-r--r--
2021-04-16 13:31
pps.h
4.06
KB
-rw-r--r--
2021-04-16 13:31
prctl.h
6.91
KB
-rw-r--r--
2021-04-16 13:31
psci.h
3.76
KB
-rw-r--r--
2021-04-16 13:31
ptp_clock.h
4.69
KB
-rw-r--r--
2021-04-16 13:31
ptrace.h
3.2
KB
-rw-r--r--
2021-04-16 13:31
qnx4_fs.h
2.21
KB
-rw-r--r--
2021-04-16 13:31
qnxtypes.h
561
B
-rw-r--r--
2021-04-16 13:31
quota.h
5.86
KB
-rw-r--r--
2021-04-16 13:31
radeonfb.h
297
B
-rw-r--r--
2021-04-16 13:31
random.h
1.2
KB
-rw-r--r--
2021-04-16 13:31
raw.h
302
B
-rw-r--r--
2021-04-16 13:31
rds.h
7.88
KB
-rw-r--r--
2021-04-16 13:31
reboot.h
1.25
KB
-rw-r--r--
2021-04-16 13:31
reiserfs_fs.h
712
B
-rw-r--r--
2021-04-16 13:31
reiserfs_xattr.h
470
B
-rw-r--r--
2021-04-16 13:31
resource.h
2.23
KB
-rw-r--r--
2021-04-16 13:31
rfkill.h
3.5
KB
-rw-r--r--
2021-04-16 13:31
romfs_fs.h
1.15
KB
-rw-r--r--
2021-04-16 13:31
rose.h
2.12
KB
-rw-r--r--
2021-04-16 13:31
route.h
2.21
KB
-rw-r--r--
2021-04-16 13:31
rtc.h
3.85
KB
-rw-r--r--
2021-04-16 13:31
rtnetlink.h
16.24
KB
-rw-r--r--
2021-04-16 13:31
scc.h
4.43
KB
-rw-r--r--
2021-04-16 13:31
sched.h
2.19
KB
-rw-r--r--
2021-04-16 13:31
scif_ioctl.h
6.15
KB
-rw-r--r--
2021-04-16 13:31
screen_info.h
2.36
KB
-rw-r--r--
2021-04-16 13:31
sctp.h
26.67
KB
-rw-r--r--
2021-04-16 13:31
sdla.h
2.71
KB
-rw-r--r--
2021-04-16 13:31
seccomp.h
1.93
KB
-rw-r--r--
2021-04-16 13:31
securebits.h
2.58
KB
-rw-r--r--
2021-04-16 13:31
selinux_netlink.h
1.11
KB
-rw-r--r--
2021-04-16 13:31
sem.h
2.88
KB
-rw-r--r--
2021-04-16 13:31
serial.h
3.15
KB
-rw-r--r--
2021-04-16 13:31
serial_core.h
5.74
KB
-rw-r--r--
2021-04-16 13:31
serial_reg.h
15.16
KB
-rw-r--r--
2021-04-16 13:31
serio.h
1.8
KB
-rw-r--r--
2021-04-16 13:31
shm.h
2.55
KB
-rw-r--r--
2021-04-16 13:31
signal.h
171
B
-rw-r--r--
2021-04-16 13:31
signalfd.h
1.07
KB
-rw-r--r--
2021-04-16 13:31
smiapp.h
995
B
-rw-r--r--
2021-04-16 13:31
snmp.h
12.58
KB
-rw-r--r--
2021-04-16 13:31
sock_diag.h
621
B
-rw-r--r--
2021-04-16 13:31
socket.h
738
B
-rw-r--r--
2021-04-16 13:31
sockios.h
5.83
KB
-rw-r--r--
2021-04-16 13:31
sonet.h
2.17
KB
-rw-r--r--
2021-04-16 13:31
sonypi.h
5.12
KB
-rw-r--r--
2021-04-16 13:31
sound.h
1.15
KB
-rw-r--r--
2021-04-16 13:31
soundcard.h
44.96
KB
-rw-r--r--
2021-04-16 13:31
stat.h
1
KB
-rw-r--r--
2021-04-16 13:31
stddef.h
1
B
-rw-r--r--
2021-04-16 13:31
string.h
175
B
-rw-r--r--
2021-04-16 13:31
suspend_ioctls.h
1.34
KB
-rw-r--r--
2021-04-16 13:31
swab.h
6.36
KB
-rw-r--r--
2021-04-16 13:31
synclink.h
8.71
KB
-rw-r--r--
2021-04-16 13:31
sysctl.h
25.49
KB
-rw-r--r--
2021-04-16 13:31
sysinfo.h
986
B
-rw-r--r--
2021-04-16 13:31
target_core_user.h
3.28
KB
-rw-r--r--
2021-04-16 13:31
taskstats.h
6.83
KB
-rw-r--r--
2021-04-16 13:31
tcp.h
5.96
KB
-rw-r--r--
2021-04-16 13:31
tcp_metrics.h
1.43
KB
-rw-r--r--
2021-04-16 13:31
telephony.h
8.84
KB
-rw-r--r--
2021-04-16 13:31
termios.h
443
B
-rw-r--r--
2021-04-16 13:31
thermal.h
861
B
-rw-r--r--
2021-04-16 13:31
time.h
1.54
KB
-rw-r--r--
2021-04-16 13:31
times.h
215
B
-rw-r--r--
2021-04-16 13:31
timex.h
6.25
KB
-rw-r--r--
2021-04-16 13:31
tiocl.h
1.63
KB
-rw-r--r--
2021-04-16 13:31
tipc.h
5.99
KB
-rw-r--r--
2021-04-16 13:31
tipc_config.h
14.35
KB
-rw-r--r--
2021-04-16 13:31
tipc_netlink.h
6.71
KB
-rw-r--r--
2021-04-16 13:31
toshiba.h
1.82
KB
-rw-r--r--
2021-04-16 13:31
tty.h
1.37
KB
-rw-r--r--
2021-04-16 13:31
tty_flags.h
4.06
KB
-rw-r--r--
2021-04-16 13:31
types.h
1.4
KB
-rw-r--r--
2021-04-16 13:31
udf_fs_i.h
634
B
-rw-r--r--
2021-04-16 13:31
udp.h
1.28
KB
-rw-r--r--
2021-04-16 13:31
uhid.h
4.48
KB
-rw-r--r--
2021-04-16 13:31
uinput.h
5.75
KB
-rw-r--r--
2021-04-16 13:31
uio.h
668
B
-rw-r--r--
2021-04-16 13:31
ultrasound.h
4.39
KB
-rw-r--r--
2021-04-16 13:31
un.h
239
B
-rw-r--r--
2021-04-16 13:31
unistd.h
157
B
-rw-r--r--
2021-04-16 13:31
unix_diag.h
1.16
KB
-rw-r--r--
2021-04-16 13:31
usbdevice_fs.h
6.43
KB
-rw-r--r--
2021-04-16 13:31
usbip.h
577
B
-rw-r--r--
2021-04-16 13:31
userfaultfd.h
4.27
KB
-rw-r--r--
2021-04-16 13:31
utime.h
152
B
-rw-r--r--
2021-04-16 13:31
utsname.h
606
B
-rw-r--r--
2021-04-16 13:31
uuid.h
1.75
KB
-rw-r--r--
2021-04-16 13:31
uvcvideo.h
1.6
KB
-rw-r--r--
2021-04-16 13:31
v4l2-common.h
2.57
KB
-rw-r--r--
2021-04-16 13:31
v4l2-controls.h
42.97
KB
-rw-r--r--
2021-04-16 13:31
v4l2-dv-timings.h
29.21
KB
-rw-r--r--
2021-04-16 13:31
v4l2-mediabus.h
4.92
KB
-rw-r--r--
2021-04-16 13:31
v4l2-subdev.h
5.89
KB
-rw-r--r--
2021-04-16 13:31
version.h
97
B
-rw-r--r--
2021-04-16 13:31
veth.h
161
B
-rw-r--r--
2021-04-16 13:31
vfio.h
20.4
KB
-rw-r--r--
2021-04-16 13:31
vhost.h
6.16
KB
-rw-r--r--
2021-04-16 13:31
videodev2.h
79.43
KB
-rw-r--r--
2021-04-16 13:31
virtio_9p.h
1.99
KB
-rw-r--r--
2021-04-16 13:31
virtio_balloon.h
3.71
KB
-rw-r--r--
2021-04-16 13:31
virtio_blk.h
5.2
KB
-rw-r--r--
2021-04-16 13:31
virtio_config.h
2.98
KB
-rw-r--r--
2021-04-16 13:31
virtio_console.h
3.06
KB
-rw-r--r--
2021-04-16 13:31
virtio_gpu.h
7.84
KB
-rw-r--r--
2021-04-16 13:31
virtio_ids.h
2.26
KB
-rw-r--r--
2021-04-16 13:31
virtio_input.h
2.45
KB
-rw-r--r--
2021-04-16 13:31
virtio_net.h
9.79
KB
-rw-r--r--
2021-04-16 13:31
virtio_pci.h
6.91
KB
-rw-r--r--
2021-04-16 13:31
virtio_ring.h
6.2
KB
-rw-r--r--
2021-04-16 13:31
virtio_rng.h
265
B
-rw-r--r--
2021-04-16 13:31
virtio_scsi.h
5.89
KB
-rw-r--r--
2021-04-16 13:31
virtio_types.h
2.11
KB
-rw-r--r--
2021-04-16 13:31
vm_sockets.h
5.13
KB
-rw-r--r--
2021-04-16 13:31
vt.h
3
KB
-rw-r--r--
2021-04-16 13:31
wait.h
600
B
-rw-r--r--
2021-04-16 13:31
wanrouter.h
390
B
-rw-r--r--
2021-04-16 13:31
watchdog.h
2.22
KB
-rw-r--r--
2021-04-16 13:31
wimax.h
8.17
KB
-rw-r--r--
2021-04-16 13:31
wireless.h
41.65
KB
-rw-r--r--
2021-04-16 13:31
x25.h
3.42
KB
-rw-r--r--
2021-04-16 13:31
xattr.h
2.62
KB
-rw-r--r--
2021-04-16 13:31
xfrm.h
11.06
KB
-rw-r--r--
2021-04-16 13:31
xilinx-v4l2-controls.h
2.84
KB
-rw-r--r--
2021-04-16 13:31
zorro.h
3.16
KB
-rw-r--r--
2021-04-16 13:31
zorro_ids.h
29.2
KB
-rw-r--r--
2021-04-16 13:31
Save
Rename
/* * V4L2 DV timings header. * * Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA * 02110-1301 USA */ #ifndef _V4L2_DV_TIMINGS_H #define _V4L2_DV_TIMINGS_H #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) /* Sadly gcc versions older than 4.6 have a bug in how they initialize anonymous unions where they require additional curly brackets. This violates the C1x standard. This workaround adds the curly brackets if needed. */ #define V4L2_INIT_BT_TIMINGS(_width, args...) \ { .bt = { _width , ## args } } #else #define V4L2_INIT_BT_TIMINGS(_width, args...) \ .bt = { _width , ## args } #endif /* CEA-861-E timings (i.e. standard HDTV timings) */ #define V4L2_DV_BT_CEA_640X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X480I59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_720X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X576I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_720X576P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1280X720P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1280X720P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1280X720P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1280X720P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1280X720P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1920X1080P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1920X1080P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1920X1080P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1920X1080I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1920X1080P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1920X1080I60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_1920X1080P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_3840X2160P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_3840X2160P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_3840X2160P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_3840X2160P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_3840X2160P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_4096X2160P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_4096X2160P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_4096X2160P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_4096X2160P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ } #define V4L2_DV_BT_CEA_4096X2160P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ } /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ #define V4L2_DV_BT_DMT_640X350P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \ 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_720X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* VGA resolutions */ #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94 #define V4L2_DV_BT_DMT_640X480P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* SVGA resolutions */ #define V4L2_DV_BT_DMT_800X600P56 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \ 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_848X480P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(848, 480, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768I43 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \ V4L2_DV_BT_STD_DMT, 0) \ } /* XGA resolutions */ #define V4L2_DV_BT_DMT_1024X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* XGA+ resolution */ #define V4L2_DV_BT_DMT_1152X864P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1152, 864, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60 /* WXGA resolutions */ #define V4L2_DV_BT_DMT_1280X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X960P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \ 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA resolutions */ #define V4L2_DV_BT_DMT_1280X1024P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \ 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1360X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1360X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1366X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1366X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA+ resolutions */ #define V4L2_DV_BT_DMT_1400X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1400X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WXGA+ resolutions */ #define V4L2_DV_BT_DMT_1440X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1440X900P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1600X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 900, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* UXGA resolutions */ #define V4L2_DV_BT_DMT_1600X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P65 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WSXGA+ resolutions */ #define V4L2_DV_BT_DMT_1680X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1680X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1792X1344P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \ 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1856X1392P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \ 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60 /* WUXGA resolutions */ #define V4L2_DV_BT_DMT_1920X1200P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1440P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \ 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2048X1152P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* WQXGA resolutions */ #define V4L2_DV_BT_DMT_2560X1600P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2560X1600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* 4K resolutions */ #define V4L2_DV_BT_DMT_4096X2160P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #endif