Gecko [ paroquia-rio-de-mouro.pt ]

Name	Size	Permission	Date
ac97_codec.h	28.3 KB	-rw-r--r--	2016-01-11 00:01
aci.h	2.36 KB	-rw-r--r--	2016-01-11 00:01
ad1816a.h	5.38 KB	-rw-r--r--	2016-01-11 00:01
ad1843.h	1.48 KB	-rw-r--r--	2016-01-11 00:01
adau1373.h	699 B	-rw-r--r--	2016-01-11 00:01
aess.h	1.63 KB	-rw-r--r--	2016-01-11 00:01
ak4113.h	10.85 KB	-rw-r--r--	2016-01-11 00:01
ak4114.h	10.18 KB	-rw-r--r--	2016-01-11 00:01
ak4117.h	8.98 KB	-rw-r--r--	2016-01-11 00:01
ak4531_codec.h	3.1 KB	-rw-r--r--	2016-01-11 00:01
ak4641.h	622 B	-rw-r--r--	2016-01-11 00:01
ak4xxx-adda.h	3.34 KB	-rw-r--r--	2016-01-11 00:01
alc5623.h	497 B	-rw-r--r--	2016-01-11 00:01
asequencer.h	3.58 KB	-rw-r--r--	2016-01-11 00:01
asound.h	1.25 KB	-rw-r--r--	2016-01-11 00:01
asoundef.h	16.7 KB	-rw-r--r--	2016-01-11 00:01
atmel-abdac.h	639 B	-rw-r--r--	2016-01-11 00:01
atmel-ac97c.h	1.31 KB	-rw-r--r--	2016-01-11 00:01
compress_driver.h	6.27 KB	-rw-r--r--	2016-01-11 00:01
control.h	8.5 KB	-rw-r--r--	2016-01-11 00:01
core.h	13.98 KB	-rw-r--r--	2016-01-11 00:01
cs4231-regs.h	8.28 KB	-rw-r--r--	2016-01-11 00:01
cs4271.h	1.38 KB	-rw-r--r--	2016-01-11 00:01
cs42l52.h	738 B	-rw-r--r--	2016-01-11 00:01
cs42l56.h	1.16 KB	-rw-r--r--	2016-01-11 00:01
cs42l73.h	507 B	-rw-r--r--	2016-01-11 00:01
cs8403.h	8.63 KB	-rw-r--r--	2016-01-11 00:01
cs8427.h	10.4 KB	-rw-r--r--	2016-01-11 00:01
da7213.h	1.15 KB	-rw-r--r--	2016-01-11 00:01
da7219-aad.h	2.42 KB	-rw-r--r--	2016-01-11 00:01
da7219.h	1.2 KB	-rw-r--r--	2016-01-11 00:01
da9055.h	914 B	-rw-r--r--	2016-01-11 00:01
designware_i2s.h	2.03 KB	-rw-r--r--	2016-01-11 00:01
dmaengine_pcm.h	5.7 KB	-rw-r--r--	2016-01-11 00:01
emu10k1.h	89.24 KB	-rw-r--r--	2016-01-11 00:01
emu10k1_synth.h	1.35 KB	-rw-r--r--	2016-01-11 00:01
emu8000.h	4.01 KB	-rw-r--r--	2016-01-11 00:01
emu8000_reg.h	10.21 KB	-rw-r--r--	2016-01-11 00:01
emux_legacy.h	5.37 KB	-rw-r--r--	2016-01-11 00:01
emux_synth.h	7.47 KB	-rw-r--r--	2016-01-11 00:01
es1688.h	3.53 KB	-rw-r--r--	2016-01-11 00:01
gus.h	20.21 KB	-rw-r--r--	2016-01-11 00:01
hda_hwdep.h	1.38 KB	-rw-r--r--	2016-01-11 00:01
hda_i915.h	1.21 KB	-rw-r--r--	2018-04-02 18:07
hda_register.h	7.92 KB	-rw-r--r--	2016-01-11 00:01
hda_regmap.h	6.45 KB	-rw-r--r--	2016-01-11 00:01
hda_verbs.h	16.73 KB	-rw-r--r--	2016-01-11 00:01
hdaudio.h	17.52 KB	-rw-r--r--	2016-01-11 00:01
hdaudio_ext.h	6.34 KB	-rw-r--r--	2016-01-11 00:01
hwdep.h	2.56 KB	-rw-r--r--	2016-01-11 00:01
i2c.h	3.47 KB	-rw-r--r--	2016-01-11 00:01
info.h	7.41 KB	-rw-r--r--	2016-01-11 00:01
initval.h	3.08 KB	-rw-r--r--	2016-01-11 00:01
jack.h	3.49 KB	-rw-r--r--	2016-01-11 00:01
l3.h	287 B	-rw-r--r--	2016-01-11 00:01
max9768.h	729 B	-rw-r--r--	2016-01-11 00:01
max98088.h	1.26 KB	-rw-r--r--	2016-01-11 00:01
max98090.h	754 B	-rw-r--r--	2016-01-11 00:01
max98095.h	1.54 KB	-rw-r--r--	2016-01-11 00:01
memalloc.h	4.41 KB	-rw-r--r--	2016-01-11 00:01
minors.h	4.33 KB	-rw-r--r--	2016-01-11 00:01
mixer_oss.h	2.45 KB	-rw-r--r--	2016-01-11 00:01
mpu401.h	4.49 KB	-rw-r--r--	2016-01-11 00:01
omap-hdmi-audio.h	1.25 KB	-rw-r--r--	2016-01-11 00:01
omap-pcm.h	864 B	-rw-r--r--	2016-01-11 00:01
opl3.h	12.41 KB	-rw-r--r--	2016-01-11 00:01
opl4.h	1.1 KB	-rw-r--r--	2016-01-11 00:01
pcm-indirect.h	5.61 KB	-rw-r--r--	2016-01-11 00:01
pcm.h	47.44 KB	-rw-r--r--	2016-01-11 00:01
pcm_drm_eld.h	144 B	-rw-r--r--	2016-01-11 00:01
pcm_iec958.h	183 B	-rw-r--r--	2016-01-11 00:01
pcm_oss.h	2.64 KB	-rw-r--r--	2016-01-11 00:01
pcm_params.h	8.96 KB	-rw-r--r--	2016-01-11 00:01
pt2258.h	1.18 KB	-rw-r--r--	2016-01-11 00:01
pxa2xx-lib.h	1.46 KB	-rw-r--r--	2016-01-11 00:01
rawmidi.h	6.2 KB	-rw-r--r--	2018-04-02 18:07
rt286.h	460 B	-rw-r--r--	2016-01-11 00:01
rt298.h	519 B	-rw-r--r--	2016-01-11 00:01
rt5640.h	648 B	-rw-r--r--	2016-01-11 00:01
rt5645.h	680 B	-rw-r--r--	2016-01-11 00:01
rt5651.h	468 B	-rw-r--r--	2016-01-11 00:01
rt5660.h	724 B	-rw-r--r--	2018-04-02 18:07
rt5670.h	652 B	-rw-r--r--	2016-01-11 00:01
rt5677.h	1.09 KB	-rw-r--r--	2016-01-11 00:01
s3c24xx_uda134x.h	212 B	-rw-r--r--	2016-01-11 00:01
sb.h	10.98 KB	-rw-r--r--	2016-01-11 00:01
sb16_csp.h	2.71 KB	-rw-r--r--	2016-01-11 00:01
seq_device.h	2.79 KB	-rw-r--r--	2016-01-11 00:01
seq_kernel.h	3.96 KB	-rw-r--r--	2018-04-02 18:07
seq_midi_emul.h	7.26 KB	-rw-r--r--	2016-01-11 00:01
seq_midi_event.h	2.17 KB	-rw-r--r--	2016-01-11 00:01
seq_oss.h	2.86 KB	-rw-r--r--	2016-01-11 00:01
seq_oss_legacy.h	1 KB	-rw-r--r--	2016-01-11 00:01
seq_virmidi.h	2.73 KB	-rw-r--r--	2018-04-02 18:07
sh_dac_audio.h	587 B	-rw-r--r--	2016-01-11 00:01
sh_fsi.h	847 B	-rw-r--r--	2016-01-11 00:01
simple_card.h	819 B	-rw-r--r--	2016-01-11 00:01
snd_wavefront.h	5.49 KB	-rw-r--r--	2016-01-11 00:01
soc-dai.h	10.11 KB	-rw-r--r--	2016-01-11 00:01
soc-dapm.h	29.24 KB	-rw-r--r--	2016-01-11 00:01
soc-dpcm.h	4.73 KB	-rw-r--r--	2016-01-11 00:01
soc-topology.h	5.45 KB	-rw-r--r--	2016-01-11 00:01
soc.h	55.55 KB	-rw-r--r--	2016-01-11 00:01
soundfont.h	4.48 KB	-rw-r--r--	2016-01-11 00:01
spear_dma.h	1003 B	-rw-r--r--	2016-01-11 00:01
spear_spdif.h	1010 B	-rw-r--r--	2016-01-11 00:01
sta32x.h	1.2 KB	-rw-r--r--	2016-01-11 00:01
sta350.h	1.65 KB	-rw-r--r--	2016-01-11 00:01
tas2552-plat.h	678 B	-rw-r--r--	2016-01-11 00:01
tas5086.h	171 B	-rw-r--r--	2016-01-11 00:01
tea6330t.h	1.14 KB	-rw-r--r--	2016-01-11 00:01
timer.h	5.39 KB	-rw-r--r--	2016-01-11 00:01
tlv.h	3.38 KB	-rw-r--r--	2016-01-11 00:01
tlv320aic32x4.h	900 B	-rw-r--r--	2016-01-11 00:01
tlv320aic3x.h	1.88 KB	-rw-r--r--	2016-01-11 00:01
tlv320dac33-plat.h	720 B	-rw-r--r--	2016-01-11 00:01
tpa6130a2-plat.h	900 B	-rw-r--r--	2016-01-11 00:01
uda134x.h	597 B	-rw-r--r--	2016-01-11 00:01
uda1380.h	481 B	-rw-r--r--	2016-01-11 00:01
util_mem.h	2.26 KB	-rw-r--r--	2016-01-11 00:01
vx_core.h	15.34 KB	-rw-r--r--	2016-01-11 00:01
wavefront.h	18.76 KB	-rw-r--r--	2016-01-11 00:01
wm0010.h	679 B	-rw-r--r--	2016-01-11 00:01
wm1250-ev1.h	656 B	-rw-r--r--	2016-01-11 00:01
wm2000.h	625 B	-rw-r--r--	2016-01-11 00:01
wm2200.h	1.46 KB	-rw-r--r--	2016-01-11 00:01
wm5100.h	1.25 KB	-rw-r--r--	2016-01-11 00:01
wm8903.h	15.16 KB	-rw-r--r--	2016-01-11 00:01
wm8904.h	7.43 KB	-rw-r--r--	2016-01-11 00:01
wm8955.h	662 B	-rw-r--r--	2016-01-11 00:01
wm8960.h	603 B	-rw-r--r--	2016-01-11 00:01
wm8962.h	1.8 KB	-rw-r--r--	2016-01-11 00:01
wm8993.h	1.19 KB	-rw-r--r--	2016-01-11 00:01
wm8996.h	1.4 KB	-rw-r--r--	2016-01-11 00:01
wm9081.h	661 B	-rw-r--r--	2016-01-11 00:01
wm9090.h	780 B	-rw-r--r--	2016-01-11 00:01
wss.h	8.44 KB	-rw-r--r--	2016-01-11 00:01

Rename

/*
 * HD-audio controller (Azalia) registers and helpers
 *
 * For traditional reasons, we still use azx_ prefix here
 */

#ifndef __SOUND_HDA_REGISTER_H
#define __SOUND_HDA_REGISTER_H

#include <linux/io.h>
#include <sound/hdaudio.h>

#define AZX_REG_GCAP			0x00
#define   AZX_GCAP_64OK		(1 << 0)   /* 64bit address support */
#define   AZX_GCAP_NSDO		(3 << 1)   /* # of serial data out signals */
#define   AZX_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */
#define   AZX_GCAP_ISS		(15 << 8)  /* # of input streams */
#define   AZX_GCAP_OSS		(15 << 12) /* # of output streams */
#define AZX_REG_VMIN			0x02
#define AZX_REG_VMAJ			0x03
#define AZX_REG_OUTPAY			0x04
#define AZX_REG_INPAY			0x06
#define AZX_REG_GCTL			0x08
#define   AZX_GCTL_RESET	(1 << 0)   /* controller reset */
#define   AZX_GCTL_FCNTRL	(1 << 1)   /* flush control */
#define   AZX_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */
#define AZX_REG_WAKEEN			0x0c
#define AZX_REG_STATESTS		0x0e
#define AZX_REG_GSTS			0x10
#define   AZX_GSTS_FSTS		(1 << 1)   /* flush status */
#define AZX_REG_GCAP2			0x12
#define AZX_REG_LLCH			0x14
#define AZX_REG_OUTSTRMPAY		0x18
#define AZX_REG_INSTRMPAY		0x1A
#define AZX_REG_INTCTL			0x20
#define AZX_REG_INTSTS			0x24
#define AZX_REG_WALLCLK			0x30	/* 24Mhz source */
#define AZX_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */
#define AZX_REG_SSYNC			0x38
#define AZX_REG_CORBLBASE		0x40
#define AZX_REG_CORBUBASE		0x44
#define AZX_REG_CORBWP			0x48
#define AZX_REG_CORBRP			0x4a
#define   AZX_CORBRP_RST	(1 << 15)  /* read pointer reset */
#define AZX_REG_CORBCTL			0x4c
#define   AZX_CORBCTL_RUN	(1 << 1)   /* enable DMA */
#define   AZX_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */
#define AZX_REG_CORBSTS			0x4d
#define   AZX_CORBSTS_CMEI	(1 << 0)   /* memory error indication */
#define AZX_REG_CORBSIZE		0x4e

#define AZX_REG_RIRBLBASE		0x50
#define AZX_REG_RIRBUBASE		0x54
#define AZX_REG_RIRBWP			0x58
#define   AZX_RIRBWP_RST	(1 << 15)  /* write pointer reset */
#define AZX_REG_RINTCNT			0x5a
#define AZX_REG_RIRBCTL			0x5c
#define   AZX_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */
#define   AZX_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */
#define   AZX_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */
#define AZX_REG_RIRBSTS			0x5d
#define   AZX_RBSTS_IRQ		(1 << 0)   /* response irq */
#define   AZX_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */
#define AZX_REG_RIRBSIZE		0x5e

#define AZX_REG_IC			0x60
#define AZX_REG_IR			0x64
#define AZX_REG_IRS			0x68
#define   AZX_IRS_VALID		(1<<1)
#define   AZX_IRS_BUSY		(1<<0)

#define AZX_REG_DPLBASE			0x70
#define AZX_REG_DPUBASE			0x74
#define   AZX_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define AZX_REG_SD_CTL			0x00
#define AZX_REG_SD_STS			0x03
#define AZX_REG_SD_LPIB			0x04
#define AZX_REG_SD_CBL			0x08
#define AZX_REG_SD_LVI			0x0c
#define AZX_REG_SD_FIFOW		0x0e
#define AZX_REG_SD_FIFOSIZE		0x10
#define AZX_REG_SD_FORMAT		0x12
#define AZX_REG_SD_FIFOL		0x14
#define AZX_REG_SD_BDLPL		0x18
#define AZX_REG_SD_BDLPU		0x1c

/* Haswell/Broadwell display HD-A controller Extended Mode registers */
#define AZX_REG_HSW_EM4			0x100c
#define AZX_REG_HSW_EM5			0x1010

/* Skylake/Broxton display HD-A controller Extended Mode registers */
#define AZX_REG_SKL_EM4L		0x1040

/* PCI space */
#define AZX_PCIREG_TCSEL		0x44

/*
 * other constants
 */

/* max number of fragments - we may use more if allocating more pages for BDL */
#define BDL_SIZE		4096
#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
#define AZX_MAX_FRAG		32
/* max buffer size - no h/w limit, you can increase as you like */
#define AZX_MAX_BUF_SIZE	(1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE	0x01
#define RIRB_INT_OVERRUN	0x04
#define RIRB_INT_MASK		0x05

/* STATESTS int mask: S3,SD2,SD1,SD0 */
#define STATESTS_INT_MASK	((1 << HDA_MAX_CODECS) - 1)

/* SD_CTL bits */
#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
#define SD_INT_COMPLETE		0x04	/* completion interrupt */
#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
				 SD_INT_COMPLETE)

/* SD_STS */
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
#define AZX_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define AZX_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define AZX_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */

/* below are so far hardcoded - should read registers in future */
#define AZX_MAX_CORB_ENTRIES	256
#define AZX_MAX_RIRB_ENTRIES	256

/* Capability header  Structure */
#define AZX_REG_CAP_HDR			0x0
#define AZX_CAP_HDR_VER_OFF		28
#define AZX_CAP_HDR_VER_MASK		(0xF << AZX_CAP_HDR_VER_OFF)
#define AZX_CAP_HDR_ID_OFF		16
#define AZX_CAP_HDR_ID_MASK		(0xFFF << AZX_CAP_HDR_ID_OFF)
#define AZX_CAP_HDR_NXT_PTR_MASK	0xFFFF

/* registers of Software Position Based FIFO Capability Structure */
#define AZX_SPB_CAP_ID			0x4
#define AZX_REG_SPB_BASE_ADDR		0x700
#define AZX_REG_SPB_SPBFCH		0x00
#define AZX_REG_SPB_SPBFCCTL		0x04
/* Base used to calculate the iterating register offset */
#define AZX_SPB_BASE			0x08
/* Interval used to calculate the iterating register offset */
#define AZX_SPB_INTERVAL		0x08
/* SPIB base */
#define AZX_SPB_SPIB			0x00
/* SPIB MAXFIFO base*/
#define AZX_SPB_MAXFIFO			0x04

/* registers of Global Time Synchronization Capability Structure */
#define AZX_GTS_CAP_ID			0x1
#define AZX_REG_GTS_GTSCH		0x00
#define AZX_REG_GTS_GTSCD		0x04
#define AZX_REG_GTS_GTSCTLAC		0x0C
#define AZX_GTS_BASE			0x20
#define AZX_GTS_INTERVAL		0x20

/* registers for Processing Pipe Capability Structure */
#define AZX_PP_CAP_ID			0x3
#define AZX_REG_PP_PPCH			0x10
#define AZX_REG_PP_PPCTL		0x04
#define AZX_PPCTL_PIE			(1<<31)
#define AZX_PPCTL_GPROCEN		(1<<30)
/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */
#define AZX_PPCTL_PROCEN(_X_)		(1<<(_X_))

#define AZX_REG_PP_PPSTS		0x08

#define AZX_PPHC_BASE			0x10
#define AZX_PPHC_INTERVAL		0x10

#define AZX_REG_PPHCLLPL		0x0
#define AZX_REG_PPHCLLPU		0x4
#define AZX_REG_PPHCLDPL		0x8
#define AZX_REG_PPHCLDPU		0xC

#define AZX_PPLC_BASE			0x10
#define AZX_PPLC_MULTI			0x10
#define AZX_PPLC_INTERVAL		0x10

#define AZX_REG_PPLCCTL			0x0
#define AZX_PPLCCTL_STRM_BITS		4
#define AZX_PPLCCTL_STRM_SHIFT		20
#define AZX_REG_MASK(bit_num, offset) \
	(((1 << (bit_num)) - 1) << (offset))
#define AZX_PPLCCTL_STRM_MASK \
	AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)
#define AZX_PPLCCTL_RUN			(1<<1)
#define AZX_PPLCCTL_STRST		(1<<0)

#define AZX_REG_PPLCFMT			0x4
#define AZX_REG_PPLCLLPL		0x8
#define AZX_REG_PPLCLLPU		0xC

/* registers for Multiple Links Capability Structure */
#define AZX_ML_CAP_ID			0x2
#define AZX_REG_ML_MLCH			0x00
#define AZX_REG_ML_MLCD			0x04
#define AZX_ML_BASE			0x40
#define AZX_ML_INTERVAL			0x40

#define AZX_REG_ML_LCAP			0x00
#define AZX_REG_ML_LCTL			0x04
#define AZX_REG_ML_LOSIDV		0x08
#define AZX_REG_ML_LSDIID		0x0C
#define AZX_REG_ML_LPSOO		0x10
#define AZX_REG_ML_LPSIO		0x12
#define AZX_REG_ML_LWALFC		0x18
#define AZX_REG_ML_LOUTPAY		0x20
#define AZX_REG_ML_LINPAY		0x30

#define AZX_MLCTL_SPA			(1<<16)
#define AZX_MLCTL_CPA			23

/*
 * helpers to read the stream position
 */
static inline unsigned int
snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
{
	return snd_hdac_stream_readl(stream, SD_LPIB);
}

static inline unsigned int
snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
{
	return le32_to_cpu(*stream->posbuf);
}

#endif /* __SOUND_HDA_REGISTER_H */