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Name
Size
Permission
Date
Action
ac97_codec.h
28.3
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2016-01-11 00:01
aci.h
2.36
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2016-01-11 00:01
ad1816a.h
5.38
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2016-01-11 00:01
ad1843.h
1.48
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adau1373.h
699
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aess.h
1.63
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ak4113.h
10.85
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ak4114.h
10.18
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2016-01-11 00:01
ak4117.h
8.98
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2016-01-11 00:01
ak4531_codec.h
3.1
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2016-01-11 00:01
ak4641.h
622
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2016-01-11 00:01
ak4xxx-adda.h
3.34
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alc5623.h
497
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2016-01-11 00:01
asequencer.h
3.58
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2016-01-11 00:01
asound.h
1.25
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asoundef.h
16.7
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2016-01-11 00:01
atmel-abdac.h
639
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2016-01-11 00:01
atmel-ac97c.h
1.31
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2016-01-11 00:01
compress_driver.h
6.58
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2021-04-13 03:05
control.h
8.64
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core.h
13.98
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2016-01-11 00:01
cs4231-regs.h
8.28
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2016-01-11 00:01
cs4271.h
1.38
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cs42l52.h
738
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cs42l56.h
1.16
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cs42l73.h
507
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2016-01-11 00:01
cs8403.h
8.63
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cs8427.h
10.4
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da7213.h
1.15
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da7219-aad.h
2.42
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da7219.h
1.2
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da9055.h
914
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2016-01-11 00:01
designware_i2s.h
2.03
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2016-01-11 00:01
dmaengine_pcm.h
5.7
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2016-01-11 00:01
emu10k1.h
89.24
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2016-01-11 00:01
emu10k1_synth.h
1.35
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2016-01-11 00:01
emu8000.h
4.01
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2016-01-11 00:01
emu8000_reg.h
10.21
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emux_legacy.h
5.37
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2016-01-11 00:01
emux_synth.h
7.47
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2016-01-11 00:01
es1688.h
3.53
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2016-01-11 00:01
gus.h
20.21
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2016-01-11 00:01
hda_hwdep.h
1.38
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2016-01-11 00:01
hda_i915.h
1.21
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2021-04-13 03:05
hda_register.h
7.92
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2016-01-11 00:01
hda_regmap.h
6.45
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hda_verbs.h
16.73
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hdaudio.h
17.52
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hdaudio_ext.h
6.34
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hwdep.h
2.56
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i2c.h
3.47
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info.h
7.41
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2016-01-11 00:01
initval.h
3.08
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2016-01-11 00:01
jack.h
3.49
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2016-01-11 00:01
l3.h
287
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2016-01-11 00:01
max9768.h
729
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2016-01-11 00:01
max98088.h
1.26
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2016-01-11 00:01
max98090.h
754
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max98095.h
1.54
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2016-01-11 00:01
memalloc.h
4.41
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2016-01-11 00:01
minors.h
4.33
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2016-01-11 00:01
mixer_oss.h
2.45
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2016-01-11 00:01
mpu401.h
4.49
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2016-01-11 00:01
omap-hdmi-audio.h
1.25
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2016-01-11 00:01
omap-pcm.h
864
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opl3.h
12.41
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2016-01-11 00:01
opl4.h
1.1
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2016-01-11 00:01
pcm-indirect.h
5.61
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2016-01-11 00:01
pcm.h
47.43
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2021-04-13 03:05
pcm_drm_eld.h
144
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2016-01-11 00:01
pcm_iec958.h
183
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2016-01-11 00:01
pcm_oss.h
2.69
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2021-04-13 03:05
pcm_params.h
9.03
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2021-04-13 03:05
pt2258.h
1.18
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2016-01-11 00:01
pxa2xx-lib.h
1.46
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2016-01-11 00:01
rawmidi.h
6.23
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2021-04-13 03:05
rt286.h
460
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2016-01-11 00:01
rt298.h
519
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2016-01-11 00:01
rt5640.h
648
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2016-01-11 00:01
rt5645.h
680
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2016-01-11 00:01
rt5651.h
468
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rt5660.h
724
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2021-04-13 03:05
rt5670.h
652
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2016-01-11 00:01
rt5677.h
1.09
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2016-01-11 00:01
s3c24xx_uda134x.h
212
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2016-01-11 00:01
sb.h
10.98
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2016-01-11 00:01
sb16_csp.h
2.71
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2016-01-11 00:01
seq_device.h
2.79
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2016-01-11 00:01
seq_kernel.h
3.96
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2021-04-13 03:05
seq_midi_emul.h
7.26
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2016-01-11 00:01
seq_midi_event.h
2.17
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2016-01-11 00:01
seq_oss.h
2.86
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2016-01-11 00:01
seq_oss_legacy.h
1
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2016-01-11 00:01
seq_virmidi.h
2.73
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2021-04-13 03:05
sh_dac_audio.h
587
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2016-01-11 00:01
sh_fsi.h
847
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2016-01-11 00:01
simple_card.h
819
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2016-01-11 00:01
snd_wavefront.h
5.49
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2016-01-11 00:01
soc-dai.h
10.11
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2016-01-11 00:01
soc-dapm.h
29.33
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2021-04-13 03:05
soc-dpcm.h
4.73
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2016-01-11 00:01
soc-topology.h
5.45
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2016-01-11 00:01
soc.h
55.55
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2016-01-11 00:01
soundfont.h
4.48
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2016-01-11 00:01
spear_dma.h
1003
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2016-01-11 00:01
spear_spdif.h
1010
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2016-01-11 00:01
sta32x.h
1.2
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2016-01-11 00:01
sta350.h
1.65
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2016-01-11 00:01
tas2552-plat.h
678
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tas5086.h
171
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tea6330t.h
1.14
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timer.h
5.39
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2016-01-11 00:01
tlv.h
3.38
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2016-01-11 00:01
tlv320aic32x4.h
900
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2016-01-11 00:01
tlv320aic3x.h
1.88
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2016-01-11 00:01
tlv320dac33-plat.h
720
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2016-01-11 00:01
tpa6130a2-plat.h
900
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2016-01-11 00:01
uda134x.h
597
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2016-01-11 00:01
uda1380.h
481
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2016-01-11 00:01
util_mem.h
2.26
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2016-01-11 00:01
vx_core.h
15.34
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2016-01-11 00:01
wavefront.h
18.76
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2016-01-11 00:01
wm0010.h
679
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2016-01-11 00:01
wm1250-ev1.h
656
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2016-01-11 00:01
wm2000.h
625
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2016-01-11 00:01
wm2200.h
1.46
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2016-01-11 00:01
wm5100.h
1.25
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2016-01-11 00:01
wm8903.h
15.16
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2016-01-11 00:01
wm8904.h
7.43
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2016-01-11 00:01
wm8955.h
662
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2016-01-11 00:01
wm8960.h
603
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2016-01-11 00:01
wm8962.h
1.8
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2016-01-11 00:01
wm8993.h
1.19
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2016-01-11 00:01
wm8996.h
1.4
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2016-01-11 00:01
wm9081.h
661
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2016-01-11 00:01
wm9090.h
780
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2016-01-11 00:01
wss.h
8.44
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2016-01-11 00:01
Save
Rename
/* * linux/sound/wm8903.h -- Platform data for WM8903 * * Copyright 2010 Wolfson Microelectronics. PLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __LINUX_SND_WM8903_H #define __LINUX_SND_WM8903_H /* * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of * zero in platform data means "don't touch this pin". */ #define WM8903_GPIO_CONFIG_ZERO 0x8000 /* * R6 (0x06) - Mic Bias Control 0 */ #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */ #define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */ #define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */ #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ #define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ #define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ #define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ #define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ #define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ /* * WM8903_GPn_FN values * * See datasheets for list of valid values per pin */ #define WM8903_GPn_FN_GPIO_OUTPUT 0 #define WM8903_GPn_FN_BCLK 1 #define WM8903_GPn_FN_IRQ_OUTPT 2 #define WM8903_GPn_FN_GPIO_INPUT 3 #define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT 4 #define WM8903_GPn_FN_MICBIAS_SHORT_DETECT 5 #define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT 6 #define WM8903_GPn_FN_FLL_LOCK_OUTPUT 8 #define WM8903_GPn_FN_FLL_CLOCK_OUTPUT 9 /* * R116 (0x74) - GPIO Control 1 */ #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ #define WM8903_GP1_PD 0x0008 /* GP1_PD */ #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ #define WM8903_GP1_PU 0x0004 /* GP1_PU */ #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ #define WM8903_GP1_DB 0x0001 /* GP1_DB */ #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ /* * R117 (0x75) - GPIO Control 2 */ #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ #define WM8903_GP2_PD 0x0008 /* GP2_PD */ #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ #define WM8903_GP2_PU 0x0004 /* GP2_PU */ #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ #define WM8903_GP2_DB 0x0001 /* GP2_DB */ #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ /* * R118 (0x76) - GPIO Control 3 */ #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ #define WM8903_GP3_PD 0x0008 /* GP3_PD */ #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ #define WM8903_GP3_PU 0x0004 /* GP3_PU */ #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ #define WM8903_GP3_DB 0x0001 /* GP3_DB */ #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ /* * R119 (0x77) - GPIO Control 4 */ #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ #define WM8903_GP4_PD 0x0008 /* GP4_PD */ #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ #define WM8903_GP4_PU 0x0004 /* GP4_PU */ #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ #define WM8903_GP4_DB 0x0001 /* GP4_DB */ #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ /* * R120 (0x78) - GPIO Control 5 */ #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ #define WM8903_GP5_PD 0x0008 /* GP5_PD */ #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ #define WM8903_GP5_PU 0x0004 /* GP5_PU */ #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ #define WM8903_GP5_DB 0x0001 /* GP5_DB */ #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ #define WM8903_NUM_GPIO 5 struct wm8903_platform_data { bool irq_active_low; /* Set if IRQ active low, default high */ /* Default register value for R6 (Mic bias), used to configure * microphone detection. In conjunction with gpio_cfg this * can be used to route the microphone status signals out onto * the GPIOs for use with snd_soc_jack_add_gpios(). */ u16 micdet_cfg; int micdet_delay; /* Delay after microphone detection (ms) */ int gpio_base; u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */ }; #endif